Emerging imaging applications are increasing in diversity. As a result of this diversity, a single image sensor, which can satisfy the requirements of all the emerging imaging applications, is increasingly difficult to design. For example, wireless multimedia sensor networks (WMSN) and disposable sensors demand low power consumption, low cost, and low data-rate, but compromise on image quality; retinal prosthesis can tolerate higher costs in exchange for low power consumption; laser Doppler imaging (LDI) needs very high sampling speed but does not need to sample every pixel. The task of designing a practical complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) which will satisfy all applications can be extremely difficult.
The data-rate problem can be partly solved by adding a dedicated digital signal processor (DSP) to compress the data, but this approach typically compromises on image quality if high compression ratios are desired. Furthermore, it is computationally intense; therefore, it introduces significant power, area, and thermal overhead. State-of-the-art DSP using commercial algorithms such as the industry standard Joint Photographic Experts Group (JPEG) codecs based on discrete cosine transform (DCT) or discrete wavelet transform (DWT) can have power consumptions on the same order as the image sensor itself. The limited processing speed of the DSP also limits its frame-rate and makes it unsuitable for high-speed applications.
Laser Doppler imaging (LDI) samples each pixel-of-interest with a bandwidth of greater than 20 kHz (>40 kSa/s) to estimate the corresponding particle flow-rate by the principle of laser Doppler (LD) effect. LD describes the difference in frequency the Doppler Shift-between the incident light and its scattered parts from moving particles. When moving particles are illuminated by a coherent light source such as a laser, the heterodyne between different copies of LD shifted back-scattered light from the ensemble of particles create a time-varying interference pattern. The first moment of the spectrum-power-density of this pattern is an estimator of the flow-rate is essentially what the LDI sensor measures.
LDI is used in a large number of industrial and biomedical instruments purposed to study liquid and gas dynamics such as blood perfusion and microcapillaries circulation. Such measurements are made non-invasive, non-contact, and instantaneous by LDI. The difficulty facing LDI is in its need to sample a large number of pixels at very high sampling rates and very high signal-to-noise ratio (SNR) under restricted thermal power budget even though not every pixel will potentially be located on blood vessels and carry flow information. Therefore, it is useful to have a sensor that is able to quickly capture a full image of the scene and analyze it to locate the pixels, which are highly likely to correspond to blood vessels and only perform LDI capture on a limited number of candidate pixels. On-chip image compression can play an important role in this scenario by shortening the transmission delay between the sensor and the processor, and it also reduces the image processing time if the compression algorithm allows the processing to be carried out directly in the compressed domain.
In a visible light communication (VLC) system, a hybrid approach of combining high fidelity (SNR) sensing with coarse compressive sensing can be utilized. In a VLC system where the receiver is a mobile camera tasked with the responsibility of locating a limited number of transmitter light-sources in the scene, the receiver performance can be enhanced by having multiple sensor readout paths each optimized for a different purpose. A compressive readout channel with low overhead can be used to scan the complete scene to maintain spatial lock to transmitter light-sources while a high SNR readout channel is multiplexed to a limited number of pixels corresponding to the transmitters, which disseminate high-speed information.
Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) are suitable for low-power applications with moderate sampling rates and resolutions at aggressively scaled technology nodes. For example, in image sensors, the steady increase in pixel resolution, frame-rate, and mobility by technology scaling has made low-power data conversion circuit design an important topic.
The main challenge of implementing an array of column parallel SAR ADCs for applications such as image sensors lies in achieving adequate resolution in a very small capacitor array given the constraints on the available circuit area. For example, a typical mismatch for a 20 fF Metal-Insulator-Metal (MIM) capacitor (minimum design rule in 0.18 μm technology) is approximately 1% standard deviation, while this figure is close to 6% for Metal-Oxide-Metal (MOM) capacitors. A bigger capacitor array results in better ADC accuracy, but the extra circuit area is prohibitively expensive in a column parallel design. Furthermore, a smaller capacitor consumes much less switching power, and also settles faster, thereby using less power in the reference generator.
The above-described background is merely intended to provide contextual overview of sensory systems in a network, and is not intended to be exhaustive. Additional context may become apparent upon review of one or more of the various non-limiting embodiments of the following detailed description.